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pb-free available sip43101 vishay siliconix document number: 72640 s-51493, rev. d?15-aug-05 www.vishay.com 1 dual output power switch with inverting input two output power switches total output drive ? 200 ma continuous 9-v to 35-v supply voltage range low side or high side switch configuration user programmable phasing of output switches internal output over voltage clamp for driving inductive loads current limit protection thermal shutdown protection uvlo with user programmable time delay

optical detectors for factory automation

sip43101 is a dual power switch ic which contains all control and power switching circuitry required to drive resistive and inductive loads in industrial applications. the output switches are npn power transistors which can be configured as either high-side or low-side switches. these switches can operate from voltages as high as 35 v and have a continuous output current rating of 200 ma, combined or individually. internal zener diodes are provided to clamp the power switch voltages to safe levels when driving inductive loads. the in1 pin is a non-inverting input which controls the output of switch 1. a 2-input exclusive or gate input controls switch 2, allowing switch 2 to be controlled by either an inverting or non-inverting control signal. sip43101 contains under voltage lockout, uvlo, a user definable turn on delay, current limit, short circuit protection, and thermal shutdown. the sip43101 is available in both standard and lead (pb)-free 16-pin tssop and powerpak mlp-44 packages, which are specified over the industrial, d suffix (?40 to 85 c) tem? perature range.

c 2 e 2 e 1 c 1 v cc fault c del gnd in 2b in 2a in 1 sip43101 r1 5 v 1 k 100 nf load load +10 to 30 v 100 nf input both switches configured as low-side, switch 2 inverted with respect to switch 1, r1 +r2 set logic high r2 gnd
sip43101 vishay siliconix www.vishay.com 2 document number: 72640 s-51493, rev. d?15-aug-05

v cc 35 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c1, e1, c2, e2 35 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c1-e1, c2-e2 (clamped by internal circuitry) 52 v . . . . . . . . . . . . . . . . . . . . . . output current continuous for one output 200 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak for one output 1.3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fault output current 10 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fault output voltage ?0.3 v t0 v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . in 1 , in 2a , in 2b ?0.3 v t0 v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ?65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating junction temperature 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation tssop-16 a @ 85 c 440 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . powerpak mlp44-16 b @ 85 c 850 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal impedance ( ja ) tssop-16 c 90 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . powerpak mlp44-16 d 47 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes a. derate 11.1 mw/ c b. derate 21.3 mw/ c c. device mounted on jedec compliant two layer test board. d. device mounted on jedec compliant four layer test board. currents are positive into, negative out of the specificed terminal. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability.
v cc 9 to 32 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating temperature range ?40 to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . .

test conditions unless specified limits parameter symbol v cc = 25 v,in1, in2 = 0 v, in1, in2, inv2 = 5 v c del = 10 nf, t a = t j min a typ b max a unit power supply supply voltage v cc 9 32 v supply current i cc ?40 to 85 c, both inputs enabled 6 9 ma logic inputs (in 1 , in 2a , in 2b ) digital input high level v ih 3.5 v digital input low level v il 1.5 v input bias current, low level i il in 1 , in 2a , in 2b = 0 v ?0.40 a input bias current, high level i ih in 1 , in 2a , in 2b = 5 v 0.02 a switches 1&2 ? high side configuration rise time (off to on) t r r load = 250 to gnd c 1 c 2 =25v 300 ns rise tiem (on to off) t f r load = 250 to gnd , c 1 , c 2 = 25 v 300 ns saturation v oltage v saths r load = 125 to gnd t a = 25 c 1.3 v saturation v oltage v saths r load = 125 to gnd t a = ?40 c 1.5 v current limit i limhs r load = 0.25 to gnd, t a = 25 c 1.1 a leakage current i lhs e 1 , e 2 = gnd, c 1 , c 2 = 25 v,in 1 , in 2a , in 2b = 0 v 5 a voltabe clamp v clhs measure (v c1 ? v e1 ) or (v c2 ? v e2 ) 52 v switches 1&2 ? low side configuration rise time (on to off) t r r load = 250 to v cc l oad =25vtoc 1 c 2 400 ns rise tiem (off to on) t f r load = 250 to v cc , l oad = 25 v to c 1 , c 2 350 ns saturation v oltage v satls r load = 125 to v cc t a = 25 c 1.3 v saturation v oltage v satls r load = 125 to v cc t a = ?40 c 1.5 v current limit i limls r load = 0.25 to v cc , t a = 25 c 1.1 a leakage current i lls e 1 , e 2 = gnd, c 1 , c 2 = 25 v,in 1 , in 2a , in 2b = 0 v 5 a voltabe clamp v clls measure (v c1 ? v e1 ) or (v c2 ? v e2 ) 52 v
16 15 14 13 1 2 3 4 12 11 10 9 5 6 7 8 v cc c 2 nc fault e 2 c del nc nc gnd e 1 in 2b nc in 2a c 1 top view in 1 tssop-16 nc nc gnd e 1 nc in 2b nc e 2 c del 12 11 10 1 2 3 94 8765 13 14 15 16 c 1 nc in 1 in 2a c 2 nc v cc fault bottom view powerpak mlp-44 sip43101 vishay siliconix document number: 72640 s-51493, rev. d?15-aug-05 www.vishay.com 3

limits test conditions unless specified v cc = 25 v,in1, in2 = 0 v, in1, in2, inv2 = 5 v c del = 10 nf, t a = t j parameter unit max a typ b min a test conditions unless specified v cc = 25 v,in1, in2 = 0 v, in1, in2, inv2 = 5 v c del = 10 nf, t a = t j symbol turn-on delay c del maximum v oltage v del 4.7 v c del threshold v delth 4 v i cdel i cdel 2.5 a fault output v cesat conducting state (on) v sdon load on fault 10 ma 0.4 v operating frequency switching frequency f sw 25 khz under voltage lockout uvlo threshold v uvlo 7.5 8 8.5 v uvlo hysteresis v hys 0.4 0.5 0.6 v thermal shutdown thermal shutdown threshold t 160 c hysteresis t hys 20 c notes a. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum (?40 to 85 c). b. typical values are for design aid only, not guaranteed nor subject to production testing and are measured at v cc = 12 v unless otherwise noted.

standard part number lead (pb)-free part number temperature range marking sip43101dq-t1 sip43101dq-t1?e3 ?40 to 85 c 43101

standard part number lead (pb)-free part number temperature range marking sip43101dlp-t1 sip43101dlp-t1?e3 ?40 to 85 c 43101
sip43101 vishay siliconix www.vishay.com 4 document number: 72640 s-51493, rev. d?15-aug-05

pin number tssop-16 mlp44-16 name function 1 15 v cc positive supply v oltage 2 16 fault open collector output that is switched low on in the event of short circuit or thermal shut down. 3 1 c del connection for the external capacitor controlling the turn on delay. 4, 10, 12, 13, 15 3, 7, 10, 11, 14 nc no connection 5 2 gnd ground pin. 6 4 in 2b input to the exclusive or controlling power switch 2. 7 5 in 2a input to the exclusive or controlling power switch 2. 8 6 in 1 input controlling power switch 1. 9 8 c 1 collector of power switch 1. 11 9 e 1 emitter of power switch 1. 14 12 e 2 emitter of power switch 2. 16 13 c 2 collector of power switch 2.

c del a capacitor connected to this pin is used to set the duration the turn on delay. the delay starts after the uvlo threshold has been reached. in 1 this pin controls the state of the output npn switch 1. a logic 0 holds the switch off while a logic 1 turns the switch on. in 2a , in 2b these pins are the inputs to the exclusive or gate that controls the state of the output npn switch 2. this allows the use of either a non-inverting or an inverted signal to control the switch. refer to the truth table for the logic function description. in 2a in 2b switch 2 low low off low high on high low on high high off e 1 this pin is the emitter of switch 1. this pin is connected to the load in the high-side switch configuration, and is connected to ground in the low-side configuration. e 2 this pin is the emitter of switch 2. this pin is connected to the load in the high-side switch configuration, and is connected to ground in the low-side configuration. c 1 this pin is the collector of switch 1. this pin is connected to the v cc in the high-side switch configuration, and is connected to the load in the low-side configuration. c 2 this pin is the collector of switch 2. this pin is connected to the v cc in the high-side switch configuration, and is connected to the load in the low-side configuration. fault this pin is an open collector output that is pulled to ground in the event of a short circuit, an overcurrent, or a thermal shut down
sip43101 vishay siliconix document number: 72640 s-51493, rev. d?15-aug-05 www.vishay.com 5

short citcuit thermal shut down reset uvlo reference control logic c 2 e 2 c 1 e 1 c del v cc fault in 2b in 2a in 1 gnd

turn on delay the turn on delay prohibits the output switches from being turned on for a period of time after v cc has passed through 8 v and the undervoltage condition no longer exists. the uvlo f unction keeps the external c del capacitor discharged until v cc is greater than 8 v. subsequently, an internal 2.5- a current source charges the capacitor from gnd to 4.7 v. a comparator detects when the voltage on c del passes through 4 v and enables the output switches. the delay time is a function of the capacitor value and is defined as 1.6 ms/nf. an external switch can be connected across the capacitor to disable the output switches and reset the time delay. short circuit and overcurrent indication when an overcurrent or short circuit condition occurs on either switch, the sip43101 enters a hiccup current limiting mode. in this mode, the capacitor on c del is discharged down to 3 v, thus turning off the output switches, and then is charged up to 4 v by a 2.5- a internal current source, thus turning the switches on again. if the overcurrent or short circuit condition remains this cycle will continue. the switches are enabled at a very low duty cycle, minimizing the power dissipation and protecting the switches from damage. the fault output will switch to gnd, indicating that an overload condition or short circuit condition exists. vishay siliconix maintains worldwide manufacturing c apability. pr oducts may be manufactured at on e of several qualified locati ons. reliability data for silicon technology and package reliability repr esent a composite of all qualified locations. for re lated documents such as package/tape drawings, par t marking, and reliability data, see http://www.vishay.com/ppg?72640 .
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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